The present invention relates to the field of digital signal processing. More specifically, one embodiment of the invention provides a means for converting a sampled representation of a time-continuous signal sampled by a first clock into a sampled representation of the time-continuous signal sampled by a second clock, where the first and second clocks are not synchronous with each other.
FIG. 1 shows one application, a communication system 10, in which the first and second clocks are typically not synchronized. Communication system 10 comprises a transmitter 12, a receiver 16, and an analog channel 14 connecting transmitter 12 to receiver 16. Transmitter 12 comprises an encoder 18, and possibly other modules not shown. Receiver 16 comprises a sigma-delta modulated (SDM) analog-to-digital converter (ADC) 20, a resampler 22, and a clock recovery means 24. Encoder 18 has an input for digital samples, an output for an analog signal, and a clock input coupled to a low frequency clock L, for timing the output of analog signal segments representing input digital samples. The analog output of transmitter 12 is an input to channel 14, which conveys the analog signal to the input of SDM ADC 20. SDM ADC 20 has a clock input driven by a high frequency clock H which is used to trigger the digital sampling of the analog signal output by channel 14 at regular intervals. The output of SDM ADC 20 is coupled to resampler 22. The output of resampler 22 is the output of communication system 10, which is the digital sample stream which was input to transmitter 12, with some delay and possibly some distortion. The output of resampler 22 is also an input to clock recovery means 24, which outputs a recovered clock L' to a second clock input of resampler 22. In alternate embodiments of communication system 10, clock L' is not recovered from the digital sample output, but is provided to resampler 22 via an external clock channel 21 from transmitter 12, or is supplied to receiver 16 by some other external clock source.
Communication system 10 is used to transfer digital samples from one point to another, over analog channel 14. Digital data is converted to an analog signal in transmitter 12, sent over analog channel 14, digitized at receiver 16, and digitally manipulated to recover the digital data originally sent. Such digital-analog systems are used for modem communications, compact disk players, digital audio tape, mobile telephones, and the like.
Typically, the digital samples take on a value selected from a set of finite possible values, where the particular value is determined by digital data which is to be transferred. For example, in a specific embodiment of a modem communication system, digital data in the form of zeroes and ones (bits) is input to a transmitter at a rate of 9600 bits per second. The transmitter selects these bits four at a time, forming a "symbol", and generates a digital value ranging from 0 to 15. An encoder within the transmitter accepts these digital symbols and outputs a segment of an analog signal associated with the digital symbol for the duration of the clock cycle. As is well known in the art, to fully recover the digital symbol, the duration of the analog segment must be at least two clock cycles of clock L. In other words, encoder 18 will output a segment representing a symbol for at least the period of two clock cycles of clock L.
However, as far as the present system is concerned, the actual symbols are not important, since these can be determined from the samples of the analog signal, if the timing is correct. For example, if two samples are taken of each analog symbol segment representing a symbol, the particular symbol can usually be determined (noise may prevent perfect recovery). However, if receiver 16 does not know where the boundaries of the analog segments are, then it is possible that samples from adjoining symbols would be combined. Thus it is important to be sampling the analog channel signal synchronized with the incoming signals, usually at a rate comparable to the clock rate L (the low frequency clock). However, this is not always possible or convenient, such as where the analog signal is sampled at a much higher rate, as is the case with SDM ADC's.
In a typical digital receiver, the analog signal is first digitized, and then the signal is manipulated by a digital signal processor or digital filter circuits. One notable difference between an analog signal and a digital signal is that the analog signal is time-continuous and amplitude-continuous. Time-continuity means that the analog signal can be measured at any point in time, and it will have a value at that point in time, whereas amplitude-continuity means that the value at the measured point in time could have an infinite number of values within a finite range. By contrast, once digitized, the analog signal is represented by a digital signal, which is a series of digital samples. The digital samples can only take on a finite number of values, usually the value closest to the sampled analog signal, and the digital signal is not defined between digital samples in the series.
As the foregoing discussion points out, a receiver must accurately sample the analog signal, minimizing the error introduced by the fact that the digital signal is a finite approximation to the analog signal. To recover the data represented by the analog signal, it is not enough to recover the signal, since the boundaries of each analog signal segment must be found. In some systems, the analog segment (of the finite set of possibilities) can be determined from a single sampling of the analog signal, at a fixed point in the analog signal segment, usually the center. Of course, to know where the center of the segment is, the clock L which the encoder used to encode the digital samples into analog signal segments, must be recovered or provided to the receiver.
In some communication systems (as in the example of FIG. 1), clock L is sent over a separate clock channel 21 from transmitter 12 to receiver 16, and in others it is provided by an external clock source (as would be the case in a digital mixer with asynchronous clocks). However, since clock channel 21 uses communication capacity, in systems where communication capacity is at a premium, clock L is recovered from the analog signal itself. In a compact disk player, for example, channels are not at a premium, so clocking information can easily be provided on a clock channel. However, for telephone data transmissions, an additional clock channel would be costly. In the digital mixer example, of two asynchronously sampled signals to be mixed, one is resampled, using the other as the resampled clock. Many methods of sending analog data signals with recoverable clock information are known. Whether the clock is transferred separately or is recoverable from the analog signal, a problem remains in that the two clocks, the sampling clock H and the signal clock L are not synchronous.
One obvious way to keep clock H and clock L in sync is to have clock H generated using a clock multiplier driven by clock L, in other words, phase-locking clock H to clock L. Since clock H is a higher frequency than clock L, the jitter of clock L is amplified at the frequency of clock H, and thus is one reason why phase-locking the clocks would be unacceptable. Lowering the frequency of clock H is not a viable solution, since clock H needs to be high so that SDM ADC 20 can oversample the analog signal to the appropriate resolution.
FIG. 2 is a block diagram of a typical resampling receiver 25, as would be used in communication system 10 (FIG. 1). Receiver 25 comprises a SDM ADC 26, a resampler 28 coupled to the output of SDM ADC 26, and a clock recovery means 29 which adjusts the phase of the clock used to resample a signal. Clock recovery means 29 receives the digital data stream output by resampler 28 and provides a phase shift value or a recovered clock to an input of resampler 28. In alternate embodiments, the clock is generated by means other than recovery from the signal itself.
SDM ADC 26 comprises a noise shaper 30 for shaping the analog input to SDM ADC 26, an A/D 32 for converting the shaped analog input to one of N digital sample levels at each clock tick (a timing point such as a rising or falling edge) of an oversampling clock input to SDM ADC 26, and a low-pass filter (LPF) 34, which filters and decimates the digital sample stream. "Analog-to-digital converter" refers to the converter itself (such as A/D 32), whereas "sigma-delta modulated analog-to-digital converter", or just SDM ADC, refers to the converter and the associated filtering conventionally associated with sigma-delta converters (such as SDM ADC 26), to the extent that filtering is used. This difference is indicated in FIG. 2, by SDM ADC 26 and A/D 32.
Resampler 28 comprises an upsampler 36 coupled to an input of resampler 28, a LPF 38 coupled to the output of upsampler 36, and a sample selector 40 coupled to an output of LPF 38. In alternate embodiments, LPF 38 is replaced with an interpolator.
Receiver 25 transforms an analog, time-continuous signal into a stream of digital samples representing the value of the analog signal at clock ticks of a clock L', as follows.
The analog signal is applied to noise shaper 30, which outputs a noise-shaped analog signal to A/D 32, as is conventional for SDM ADC's. A/D 32 samples the input analog signal at a clock rate H which is much higher (oversampling) than the Nyquist rate for the input analog signal (twice the bandwidth). The output of A/D 32 is fed back to noise shaper 30 through a digital-to-analog converter (D/A) 41. Noise shaper 30 shapes the analog signal to reduce the quantization error noise caused by A/D 32 sampling the amplitude-continuous input analog signal at only N levels (typically N=2 or 3). The quantization noise is reduced by sampling the input signal at a high rate, moving the noise (using the noise shaper) to a higher frequency range than the signal bandwidth, and then low-pass filtering the signal to eliminate the high frequencies containing the noise.
LPF 34 filters away the high frequencies, and decimates the data sampling rate by a factor of D, to attain a sampling rate comparable to twice the signal bandwidth. The decimation to a clock rate of H/D is done to simplify processing of the digital samples, as their number is reduced by a factor of D, and also to eliminate redundancy of digital samples representing a band-limited signal. The decimation does not result in loss of information, since the analog signal is band-limited to frequencies below (1/2 * H/D). Using a sinc filter comprising N integrators, a decimator, and N differentiators reduces hardware needs by a factor of roughly D/2, however such a filter introduces a fixed decimation phase, which is an undesired side effect when resampling to a different, and possibly varying, sampling phase.
Since the digital samples at clock rate H/D output by SDM ADC 26 do not coincide with the ticks of clock L (since H, or H/D, and L are independent of each other), the signal must resynchronized to the original clock L. This is done in receiver 25 by resampling the signal with a new clock, L', which is phase-locked to the original clock L. Since the ticks of clock L and H/D are not necessarily coincident in time because of the interclock drift, the values of the analog signal at the ticks of clock L' are not available directly from the digital samples at clock rate H/D.
Resampler 28 provides these values at the clock L' ticks, by estimating the value of the time-continuous analog signal for the times of the clock L' ticks from the samples of the signal at the clock H/D ticks, which are available at the output of SDM ADC 26. FIG. 3, discussed below, illustrates the resampling process.
A typical low frequency clock L for a modem is 9600 or 19200 hertz, and a typical high frequency clock H is 2.5 megahertz (or 2,457,600 hertz, with D=128 or 256), or higher if the receiver can process data at a high rate. Clock H is typically derived by a stable crystal oscillator. Although clock L might originally also derive from a stable oscillator, the clock L oscillator is free to drift relative to clock H, since the oscillators are independent. Furthermore, changes in the analog channel delay introduce apparent drifts of clock L. Where the original clock L is recovered at receiver 25 from the analog signal, the recovered clock will cancel out any jitter caused by channel delay, but the jitter on clock L' will cause noise problems if clock H is tied to clock L'.
FIG. 3(a) is a graph of the time-continuous analog signal applied to SDM ADC 26. FIG. 3(b) is a graph of the output of SDM ADC 26, which comprises digital values sampled at discrete times at a rate of H/D. FIG. 3(e) is a graph of digital values representing samples of the analog signal at times coincident with ticks of clock L'. FIGS. 3(c)-(d) show on method of deriving the values at clock L' from the values at clock H/D.
FIG. 3(c) is a graph of the output of upsampler 36, where digital samples with zero values are interleaved between samples at clock rate H/D to increase the number of samples.
FIG. 3(d) is a graph of the output of LPF 38, overlaid with a graph of the original analog signal. Although the additional samples in FIG. 3(d) do not exactly sample the original analog signal, they are close because the analog signal is a band-limited signal limited to frequencies below (1/2 * H/D). The digital samples in FIG. 3(e) are computed by interpolation of a number (in this case, 3) of the upsampled and low-pass filtered samples.
As shown in FIG. 2, when a SDM ADC and a resampler are combined, the digital signal is downsampled, filtered, upsampled, and re-filtered, all resulting in a loss of accuracy and consuming unnecessary signal processing resources. The input analog signal is first digitized at one clock rate, H, downsampled to another, H/D, upsampled to yet another, U * (H/D), and then resampled to a clock rate L'. From the above it is seen that an improved means for resampling sampled signals at an arbitrary phase is needed.